1. FIELD OF THE INVENTION
This invention relates to resistors in integrated circuits and, more specifically, to integrated circuit resistors having balanced field plates connected thereto.
2. BRIEF DESCRIPTION OF THE PRIOR ART
The formation of resistors as parts of integrated circuits on a chip is a long established art. However, in the formation of such resistors in integrated circuits, there has been a serious stability problem with the resistor values and the ability to maintain the parameter values of matched resistors the same during circuit operation. The value of diffused or implanted resistors in silicon integrated circuits can be affected by electrostatic fields around the body of the resistor. Any variation in these fields, such as would be caused by mobile ion movement, or by polarization of the surface oxide/phosphosilicate glass layers over the resistors, can change the parameter values of the resistors. In circuit designs using matched components, shifting resistor values can lead to operating problems, such as, for example, threshold shifts or common mode voltage sensitivity.
The use of field plates is well known for use in connection with bipolar integrated circuits to prevent parasitic PMOS formation. The parasitic PMOS if formed between adjacent p-type regions by the inversion of the lightly doped n-type epitaxial layer separating the p-type regions. This inversion of the epitaxial layer can be caused, for example, by a negative potential applied to a metal interconnect lead crossing over the epitaxial layer or by an accumulation of negative charges in or on the oxide layer covering the epitaxial layer. If this parasitic PMOS device becomes active due to the inversion and conducts current, then the operation of the designed device will be impaired.
Field plates designed for parasitic PMOS elimination comprise an extension of the metalization layer tied to the p-type region. The metal extends over the epitaxial layer beyond the p-type region/epitaxial layer junction. The field plate metalization is connected electrically to the p-type region with the more positive electrical potential, which is the source terminal of the parasitic PMOS. The metal extending out over the epitaxial layer forms the gate terminal of the parasitic PMOS. The metal gate is extended out over the epitaxial region a distance which is sufficient to withstand the applied voltage. The electrical connection of the gate terminal to the source terminal keeps the parasitic PMOS turned off. This means that there is no current flow from the source terminal, up to the breakdown voltage of the device.
In oxide sidewall isolated processes, such as those using insulating silicon dioxide for isolation between adjacent circuit regions rather than the older traditional junction diode isolation, the p-type region source terminals of parasitic PMOS transistors can be surrounded by isolation oxide. There is a potential path for parasitic PMOS formation under the isolation oxide, but the voltages required to turn on the parasitic PMOS are much higher than in the junction isolated case. This is due to the greater thickness of the isolation oxide, compared with the thickness of normal oxide over epitaxial layers. Because of this, the need for the traditional field plates is reduced or eliminated.
Another surface charge and inversion problem can occur which will not be solved through the use of traditional field plates. In lightly doped p-type region resistors, wherein there is greater susceptibility to stability problems, changing surface charge conditions can modulate the resistor values. This is an action similar to a depletion mode MOS device, since the p-channel exists under conditions of no bias.
This change of resistor values can be a significant or fatal problem in circuits whose operation is dependent upon close matching or ratioing of component values, such as in linear differential line receivers.